
Support customized PID, VID by external EEPROM/ SMBUS/

Backward compatible to USB specification Revision 1.1 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) Downstream ports support HS, FS, and low-speed (LS) traffic Upstream port supports both high-speed (HS) and full-speed (FS) traffic

Compliant to USB Specification Revision 2.0.For the detailed configuration methods, please refer to the following table. Number of downstream ports and non/removable downstream port can be configured by different ways, such as EEPROM, SMBUS or I/O strapping. GL850G-60 is a full function solution which supports both Individual and Gang (4 ports as a group) mode for power management (Individual mode is only available in QFN28 package). are easily achieved by programming the external EEPROM or SMBUS mode. The complicated settings such as PID, VID, and number of downstream ports settings…etc. GL850G-60 provides better design flexibility for customers. Default settings in the internal mask ROM is responded to the host without having external EEPROM. Firmware of GL850G-60 will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. GL850G-60 embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. GL850G-60 integrates both 5V to 3.3V and 3.3V to 1.8V low dropout voltage regulator into single chip, therefore no external LDO required. GL850G-60 provides multiple advantages to simplify board level design that help achieving lowest BOM (Bill of Material) for system integrator. GL850G-60 has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide.

GL850G-60 inherits Genesys Logic's cutting edge technology on cost and power efficient serial interface design. GL850G-60 is Genesys Logic's advanced STT hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0.
